ADCLK948

数据手册 1

• ADCLK948: Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer Data Sheet (Rev.B) 06/02/2010

用户手册 1

• UG-068: Setting Up the Evaluation Board for the ADCLK948 11/16/2009

技术文章 4

• 使用具有精密相位控制的超宽带PLL/VCO替代YIG调谐振荡器硅片 04/01/2015

• Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems 12/07/2004

• Design A Clock-Distribution Strategy With Confidence 04/27/2006

• Speedy A/Ds Demand Stable Clocks 03/22/2004

常见问题 1

• FAQ 10/25/2019

参考电路 1

• CN0294：利用低抖动LVPECL扇出缓冲器增加时钟源的输出数 09/20/2012

教程 1

• MT-008: 将振荡器相位噪声转换为时间抖动 03/05/2009